TTSH Arp 2600

Matching of the PNP/NPN transistors is at last done! Here is the triple-heart of ARP 2600 ready to go the mother board (three VCO's). Matched transistors hug each other and are in contact with the tempco resistors (middle down at the board). More matched transistors are needed in filter and VCA's.

Pseudo Random Generator simulation with LogiSim

I have been working with Pseudo Random Generators (PRG) PCB layouts. I didn't find a suitable protoboard so I decided to built my own two layer protoboards. That has taken me a quite a long time but now it is almost done. I also decided first to simulate PRG with LogiSim www.cburch.com/logisim/. LogiSim is a free Java-based software. I found from web the basic TTL-chip libraries for LogiSim. The Odd/Even Parity Generator 74180 I didn't find so I had to build it from the basic logic gates as a sub circuit (pictured below).

74180 parity generator

Here below you can see the PRG circuit in LogiSim. In the middle-left there is the 24-bit shift-register build from three cascaded 74164 8-bit shift-registers. Right from the shift-register is 24-bit odd/even generator from three 74180 modules. Up are the switches (LogiSim constants) where you can choose the XOR/feedback points for the LFSR sequence. Down-left are 24 LED's that show the shift-registers bits. Right from the LED's is the start-logic that handless the non-allowed zero status. Right there is the Sync-module (also pictured here below separately) that identifies the start/end of the sequence and blinks a LED whenever this happens. This simulation works and is a proof of the concept so that I can go ahead with the PCB-layout.

PRG-circuit

 

Sync-generator

New Pseudo Random Generator

I have been thinking my Buchla quantized voltages project a lot and decided to move it another direction. I am going to build a Pseudo Random Generator (PRG) that is mostly based on a great IEEE-article "A Versatile Pseudo-Random Noise Generator" by Lipson,Foster and Walsh http://core.kmi.open.ac.uk/download/pdf/10211576.pdf. I will modify their circuits to 24bits and merge it with Bernie Hutchins Capture Wheel idea http://electronotes.netfirms.com/EN76.pdf. With it's Feedback-generator logic PRG can generate any shift-register sequence between 1-24. PRG has 24bit Gaussian stepped voltage output that is generated with digital sinc(x) filter (sinx/x). This filter has the rectangular shape in frequency domain which means the output is ideal white noise with Gaussian distribution (see also Hewlett-Packard's Model 3722A Noise Generator documentation http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1967-09.pdf). I made a simple Excel-sheet that calculated the 24 resistor values needed for sinc(x) weighted summation. You need only 12 different resistor values because the filter is symmetrical between point y=1 (see picture below). You can leave the 6th and 19th resistors out because at y=0 the weighting/gain is 0. Here is also a block diagram of PRG where the blue-boxes will be implemented first. With TTL-logic circuits this implementation is quite complex. The core needs four separate boards. It's all TTL-implementation except the digital-filter board whit the summing OP Amp. With Sync-generator board it is possible to count with this circuit to maximum of 2^24-1=16 777 215 !